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July 10, 2005
OC-192/STM-64 SFF Transponder
(1550nm, 40/80km transmission)
Members of Softac Family
Standard
Compliant with 300-PIN MSA Compliant with ITU-T G.691 Compliant with ITU-T G.959.1 Compliant with Telcordia GR-253 Compliant with IEEE 802.3ae Compliant with OIF SFI-4 interface
Features
Compliant with the 300 pin MSA in a compact size Support transmission distance of 40km and 80km Support multi-rate operation from 9.953Gb/s to 11.318 Gb/s DWDM externally EA modulated laser Wide dynamic range InGaAs PIN ror APD eceiver 1:16 MUX/DEMUX integrated 16-bit parallel 622.08Mbps LVDS data interface Selectable dual fixed-rate jitter clean-up which can be bypassed for multi-rate operation Compliant I2C MSA (Edition 4.0) interface for monitoring/control Supply voltage: +1.8V, +3.3V, +5.0V, -5.2V Operating case temperature: -5 to +70
Compliant with Telcordia GR-468-Core Compliant with IEC-60825-1 Class
Description
The transponders are intended for 1550nm system applications with reaches of up to 40km and 80km, which is designed to provide high optical performance for SONET OC-192 / SDH STM-64. The transmitter converts the electrical data into 10Gbit/s circuit. At the receiving side, the incoming data stream is received at 10Gb/s PIN or APD receiver, which converts it into a 10Gb/s electrical data stream. The MUX section multiplexes 16 parallel 622Mb/s electrical channels into a 10Gb/s series data stream and sent it to the transmitter. And the DEMUX section demultiplexes the 10Gb/s electrical data stream into 16 parallel 622Mb/s electrical channels. The parallel data is sent out to and get from the 300-pin MSA (Multi Source Agreement) compliant connector. The transmitter and receiver reference clock rates are selectable for divide by 16 or 64. optical signal, which uses 1550nm externally EA modulated laser with specified driving
Applications
Metro network SDH / SONET system 10 Gigabit Ethernet system Forward Error Correction (FEC) system Optical Transport Network (OTN) System
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Block Diagram
LsENABLE APC TxDIN[0:15]P/N TxPICLKP/N TxREFCLKP/N TxREFSEL TxRESET TxFIFORES TxRATESEL0/1 TxPCLKP/N TxMCLKP/N TxLOCKERR TxFIFOERR RxDOUT[0:15]P/N RxPOCLKP/N RxMCLKP/N RxREFCLKP/N RxREFSEL RxLCKREF RxRATESEL0/1 RxLOCKERR RxALIMINT TxALIMINT ALMINT
16 16
LsPOWMON LsBIASMON LsPOWALM LsBIASALM
MUX with CMU
Driver
TX E-O
OC-192 Optical Output
ATC
LsTEMPMON LsTEMPALM
Serial Monitor DEMUX with CDR
I2CDATA I2CCLOCK OC-192 Optical Iutput RxPOWMON RxPOWALM
RX O-E
Optical Monitor
+5.0V
+3.3V +1.8V
-5.2V
GND
Figure 1, Block Diagram of Transponder
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Absolute Maximum Ratings
Stresses in excess of the Absolute Maximum Ratings can cause permanent damage to the device. Table 1- Absolute Maximum Ratings Parameter Storage Temperature Operating Case Temperature Symbol TS Tcm Vcc Supply Voltage Vdd1 Vdd2 Vee Operating Relative Humidity (non-condensing) Electro-Static Discharge Input Optical Power PIN APD RH ESD Pin Min. -40 -10 -0.5 -0.5 -0.5 -7.0 Max. +85 +75 +6.0 +4.2 +3.3 +0.5 85 2000 +3 +1 Unit C C V V V V % V dBm
Recommended Operating Conditions
Specified performance is maintained over all conditions in the table below, and damage to the device may occur over an extended period of time. Table 2 - Recommended Operating Conditions Parameter Operating Case Temperature Symbol TC Vcc Supply Voltage Vdd1 Vdd2 Vee Icc Supply Current Idd1 Idd2 Iee Power consumption Power supply noise rejection Pd Min. -5 4.75 3.13 1.62 -5.46 5.0 3.3 1.8 -5.2 100 300 700 450 5.00 Typ. Max. +70 5.25 3.46 1.98 -4.94 150 750 850 600 7.00 50 Unit C V V V V mA mA mA mA W mVp-p
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Optical Interface Characteristics
Table 3 - Optical Characteristics Parameter Centre Wavelength Wavelength Accuracy Output Power Output Power Stability Output Power at laser disable Spectral Width (-20dB) Side Mode Suppression Ratio Extinction Ratio Chromatic Dispersion Output Optical Eye Jitter Generation 40km 80km 40km 80km G.691 B1 B2 Receiver Centre Wavelength Receiver Sensitivity Receiver Overload Optical Path Penalty Reflection of Receiver Jitter Tolerance Jitter Transfer Notes: 1. The optical power is launched into SMF. 2. Measured with a NRZ PRBS 231-1 test pattern @ 9.95328Gbps. 3. Measured with a NRZ PRBS 231-1 test pattern @ 9.95328Gbps, BER 1x10-12. PIN APD PIN APD C Pin Pin -1 -6 1290 -19 -26 0 -5 2 -27 1600 -17 -24 nm dBm dBm dB dB 3 3 0.3 0.1 UI UI 2 2 P0ut 20 SMSR ER 35 9 10 800 1600 Symbol C C P0ut Min. 1528 -0.1 -1 -0.5 Typical Max. 1563 +0.1 +2 +0.5 -45 0.3 Unit nm nm dBm dBm dBm nm dB dB ps/nm 1 Notes Transmitter
Compliant with Telcordia GR-253-CORE and ITU-T
Compliant with Telcordia GR-253 and ITU-T G.825 Compliant with Telcordia GR-253 and ITU-T G.825
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Electrical Interface Characteristics
Table 4 - LVDS Input/Output Specification Parameter LVDS interface Input Differential Voltage Input Differential impedance Output Differential Voltage Output Common Mode Voltage Output Differential impedance Rise Time/Fall time Clock Signal Duty Cycle VID RID VOD VCMO ROD Trise/fall 45 50 80 100 120 250 55 ps % 200 80 500 100 120 1000 mV mV Symbol Min. Typical Max. Unit Notes
VP Differantial Voltage (VOD or VID) VN Definition of Differantial Voltage Levels
Table 5 - Input Reference Clocks Parameter Input Differential Voltage Differential Input Impedance Clock signal Duty Cycle Symbol VID RID Tw/To Min. 400 80 45 100 Typical Max. 1800 120 55 % Unit mV Notes
Common Mode Voltage (VCMI or VCMD)
Table 6 - LVTTL Input/Output Pin Characteristics Parameter Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Symbol Min. 2.0 GND 2.4 GND Typical Vdd 0.8 Vdd 0.4 Max. Unit V V V V Notes
Transponder Clock Interfaces and Control
There are seven clock interfaces to the transponder. This section details the specific functions, capabilities, and limitations of each. Note that all clock rates shown are at STM-64/OC-192 rate, but should be scaled appropriately for other data rates. The LVPECL TxREFCLK, provided via the 300-pin interface, may be at 1/16 or 1/64 of the transmitted serial data rate. The TxREFCLK must be synchronous with the TxPICLK. There are several approaches to ensure this synchronous relationship. The two most common are
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1) locking the TxPICLK to the TxPCLK out of the transponder 2) generating TxPICLK and TxREFCLK from the same clock on the line-card. The LVPECL RxREFCLK may be at 1/16 or 1/64 of the incoming data rate also. Table 7 - Reference Clock characteristics Parameter Symbol TxREFCLKP TxREFCLKN Min. Typical Max. Unit Notes Transmitter Frequency Frequency tolerance Rise/Fall time Duty Cycle RxREFCLKP RxREFCLKN Tr/Tf 40 50 155.52/622.08 -100 +100 300 60 Receiver Frequency Frequency tolerance Rise/Fall time Duty Cycle Tr/Tf 40 50 155.52/622.08 -100 +100 300 60 MHz ppm ps % Serial data-rate is 9.953Gbps MHz ppm ps % Serial data-rate is 9.953Gbps
Table 8 - Transmitter/Receiver Parallel Data/Clock Interface Parameter Transmitter 16-bit parallel Date Input Transmitter Source synchronous ParallelInput Clock Transmitter Counter Clock Receiver 16-bit parallel Date Output Receiver Source synchronous Parallel Output Clock Symbol TxDin[0:15]P/N TxPICLKP/N TxPCLKP/N RxDout[0:15]P/N RxPOCLKP/N Level LVDS LVDS LVDS LVDS LVDS RxDout0:LSB, RxDout15:MSB Notes TxDin0:LSB, TxDin15:MSB
Table 9 - Transmitter/Receiver Parallel Data/Clock Timing Parameter Duty Cycle Rise and Fall time Setup time Hold time Symbol Tw/To Tr/Tf Ts Th 300 300 Min. 40 Typical Max. 60 300 Unit % ps ps ps 20 - 80% Notes
Transmitter Data/Clock Timing: SERDES Input Timing at SERDES pin TxPICLK TxDin
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To TxPICLKP Tw
TxDin[0:15]P/N
Ts
Th
Ts: Measuring from the LHS inner data eye to the immediate rising edge of clock pulse Th: Measuring from the rising edge of clock pulse to the inner RHS of data eye
Receiver Data/Clock Timing: SERDES Output Timing at SERDES pin RxPOCLK RxDout Duty cycle Rise and Fall time Data/Clock skew Tw/To Tr/Tf Tcq_min, Tcq_max
To RxPO CLKP Tw
40
60 300 250 250
% ps ps ps 20 - 80%
Tcq_m ax R x D o u t[0 :1 5 ]P /N
T c q _ m in
Table 10 - Monitor Clock Parameter Transmitter monitor clock Receiver monitor clock TxMCLKP/N LVDS Symbol Level Notes The LVDS TxMCLK is either a 1/16 or 1/64 replica of the clock used to time the serial data output. The rate of the TxMCLK is always the same as that of the TxREFCLK RxMCLKP/N LVDS The LVDS RxMCLK is a 1/16 or 1/64 replica of the clock recovered from the incoming data
Table 11 - Serial Data Rate selection (LVTTL with pull-up resistor) TxRATESEL1/ RxRATESEL1 L L H H TxRATESEL0/ RxRATESEL0 L H L H Function Tx/Rx Serial Data Rate 10.3125Gbps 11.049/11.095/ 11.318Gbps 10.519/10.664/ 10.709Gbps 9.95328Gbps Parallel Data Rate TxDIN[0:15]/RxOUT[0:15] 644.54Mbps 690.56/693.43/ 707.37Mbps 657.43/666.51/ 669.32Mbps 622.08Mbps TxPICLK/RxPOCLK 644.54Mbps 690.56/693.43/ 707.37Mbps 657.43/666.51/ 669.32Mbps 622.08Mbps
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Digital Control Signal
Table 12 - Input Digital signals Function Module RESET Diagnostic Loop-back Line Loop-back Transmitter 0,0 Select data rate serial 0,1 TxRATESEL1, 0 LVTTL 1,0 1,1 Select frequency TxREFCLK Select frequency TxPICLK Enable internal Line Timing Select delay of TxPICLK TxSKEWSEL0,1 LVTTL TxLINETIMSEL LVTTL the of TxPICLKSEL LVTTL H L H 0,0 0,1 1,0 1,1 Enable/Disable Laser Asynchronous system reset LsENABLE TxRESET LVTTL LVTTL L H L H L MUX reset FIFO TxFIFORES LVTTL H Low freyuency transmitter input Tx_TRACE Analog (0~2.5V) Normal operation AC-coupled low frequecy transmitter input 1/32 data-rate Enable Normal operation Delays 915ps Delays 1015ps Delays 715ps Delays 815ps Normal operation Laser disabled MUX reset Normal operation MUX FIFO reset (LVTTL with pull-down resistor) (LVTTL with pull-up resistor) Internally the TxFIFORES is connected to TxFIFOERR. TxFIFOERR will initiate a FIFO reset (LVTTL with pull-up resistor) (LVTTL with pull-up resistor) On multi-rate units without jitter clean up, this pin is ignored. (LVTTL with pull-up resistor) the of TxREFSEL LVTTL H L 1/16 data-rate 1/16 data-rate (LVTTL with pull-down resistor) L 10.3125Gbps 11.049/11.095/ 11.318Gbps 10.519/10.664/ 10.709Gbps 9.95328Gbps 1/64 data-rate (LVTTL with pull-up resistor) (LVTTL with pull-up resistor) DLOOPENB LVTTL Symbol MOD_RESET Level LVTTL L H L H LLOOPENB LVTTL L H Description Module reset Normal operation Enable Normal operation Enable Normal operation (LVTTL with pull-up resistor) Note Reset both Tx and Rx section (LVTTL with pull-up resistor) (LVTTL with pull-up resistor)
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Receiver 0,0 Select rate data 0,1 TxRATESEL1,0 LVTTL 1,0 1,1 Select frequency RxREFCLK Select frequency RxMCLK Lock RxPOCLK RxREFCLK Mutes the RxMUTEDOUT LVTTL RxDOUT[0:15] Mutes the RxMUTEMCLK LVTTL to RxLCKREF LVTTL the of RxMCLKSEL LVTTL H L H L H receiver output monitor clock Mutes receiver parallel output clock RxPOCLK Rx synchronous system reset Low freyuency receiver output Tx_TRACE Analog (20V/mA) RxRESET LVTTL RxMUTEPOCLK LVTTL H Normal operation Asynchronous reset Normal operation AC-coupled low frequecy receiver output Long reach modules support only (LVTTL with pull-up resistor) L H L 1/16 data-rate Lock to RxREFCLK Normal operation Mutes the RxDOUT[0:15] Normal operation Mutes the RxMCLK Normal operation Mutes the RxPOCLK (LVTTL with pull-up resistor) (LVTTL with pull-up resistor) (LVTTL with pull-up resistor) (LVTTL with pull-up resistor) the of RxREFSEL LVTTL L H L 10.3125Gbps 11.049/11.095/ 11.318Gbps 10.519/10.664/ 10.709Gbps 9.95328Gbps 1/64 data-rate 1/16 data-rate 1/64 data-rate (LVTTL with pull-up resistor) (LVTTL with pull-down resistor) (LVTTL with pull-up resistor)
L H
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Digital Alarm Signal
Table 13 - Alarms Digital signals Function Symbol Level Description Any alarm from Indicates alarm active Transmitter Loss of Tx PLL lock L TxLOCKERR LVTTL H L MUX FIFO error TxFIFOERR LVTTL H Alarm active Normal operation Alarm active (FIFO overflow) Normal operation Alarm active L Laser bias out of range LsBIASALM LVTTL H Laser temperature out of range Laser power range Tx alarms Receiver Loss of Rx PLL lock Loss of receiver average power alarm Rx alarms RxALMINT LVTTL RxPOWALM LVTTL RxLOCKERR LVTTL L H L H L H Alarm active Normal operation Alarm active Normal operation Alarm from transmitter Normal operation Activation Time: 1ms Deactivation Time: 1ms Activation Time: <1ms Deactivation Time: <1ms Activation Time: 10 ms; Deactivation Time: 10 ms TxALMINT LVTTL output out of LsPOWALM LVTTL LsTEMPALM LVTTL L H L H L H (laser bias current alarm) Normal operation Alarm active Normal operation Alarm active Normal operation Alarm from transmitter Normal operation Loss of transmitter PLL lock Activation Time: 1ms Deactivation Time: 1ms TxError is internally connected to TxFIFO RES. (Default) Customer may have control of TXFIFO RES without internal loopback (Optional) Alarm when laser bias changes by a factor of 2 from beginning of life or if monitor reaches maximum level corresponding to approximate150mA. Activation Time: 10 ms Deactivation Time: 10 ms Laser temperature 5C from nominal, Activation Time : 10ms Deactivation Time : 10ms Output power degrades 3dB below the BOL Activation Time : 10ms Deactivation Time : 10ms Activation Time: 10 ms; Deactivation Time: 10 ms all ALMINT LVTTL L H both transmitter and receiver Normal operation Activation Time: 10ms Deactivation Time: 10ms Note Common Digital Signal
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Analog Monitoring Signal
Table 14 - Monitor Signals Function Transmitter Normalized laser power monitor voltage BOL Laser power monitor voltage slope Laser bias monitor voltage offset Laser bias monitor voltage slope Normalized laser temperature Monitor voltage Laser temperature Monitor voltage slop Receiver Input optical power monitor voltage slope-PIN Input optical power monitor voltage slope-APD Input optical power monitor error RxPOWMON -1.5 1.0 8.0 +1.5 V/mW V/mW dB LsPOWMON 0.47 0.5 (mW) LsBIASMON LsTEMPMON 0.2 18 2.4 23 0 20 2.5 25 2 22 2.6 27 V mV/mA V mV/ 0.53 V 0.25 V change for 50% power variation Symbol Min. Typ. Max. Unit
I2C Serial Interface
Table 14 - I2C Interface Function Symbol I2CAD0 I2C Address I2CAD1 I2CAD2 I2C Clock I2C Data I2CCLOCK I2CDATA Level LVTTL LVTTL LVTTL Open collector Open collector Description I2C address input for module addressing (LSB) I2C address input for module addressing I2C address input for module addressing (MSB) I2C clock input/output for remote access I2C data input/output for remote access Note (LVTTL with pull-down resistor) (LVTTL with pull-down resistor) (LVTTL with pull-down resistor) N/A N/A
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Pin Definitions
Table 15 - Pin Function Definitions
K 1 2 3 4 5 6 7 8 +5V +5V J RxTRACE FFU H GND GND FFU GND GND DLOOPENB GND GND FFU GND GND FFU GND GND FFU GND GND FFU GND GND FFU GND GND FFU GND GND LLOOPENB GND GND LINETIMESEL G RxDout12P RxDout12N GND RxDout13P RxDout13N GND RxDout14P RxDout14N GND RxDout15P RxDout15N GND FFU FFU GND TxDin12P TxDin12N GND TxDin13P TxDin13N GND TxDin14P TxDin14N GND TxDin15P TxDin15N GND TxPICLKP TxPICLKN GND F +1.8V +1.8V RxPOWMON +3.3V +3.3V RxPOWALM +3.3V +3.3V FFU -5.2V -5.2V FFU -5.2V -5.2V RxREFSEL +1.8V +1.8V LsBIASMON +3.3V +3.3V LsENABLE +3.3V +3.3V LsBIASALM -5.2V -5.2V LsTEMPALM -5.2V -5.2V TxREFSEL E RxDout8P RxDout8N GND RxDout9P RxDout9N GND RxDout10P RxDout10N GND RxDout11P RxDout11N GND RxPOCLKP RxPOCLKN GND TxDin8P TxDin8N GND TxDin9P TxDin9N GND TxDin10P TxDin10N GND TxDin11P TxDin11N GND TxPCLKP TxPCLKN GND D GND GND I2CAD0 GND GND I2CAD1 GND GND I2CAD2 GND GND MOD RESET GND GND FFU GND GND LsPOWMON GND GND LsTEMPMON GND GND FFU GND GND FFU GND GND LsPOWALM C RxDout4P RxDout4N GND RxDout5P RxDout5N GND RxDout6P RxDout6N GND RxDout7P RxDout7N GND RxMCLKP RxMCLKN GND TxDin4P TxDin4N GND TxDin5P TxDin5N GND TxDin6P TxDin6N GND TxDin7P TxDin7N GND TxMCLKP TxMCLKN GND B GND GND RxDTV GND GND RxMUTE Dout GND GND RxLCKREF GND GND RxMCLKSEL GND GND RxLOCKERR GND GND TxSKEWSEL0 GND GND TxSKEWSEL1 GND GND FFU GND GND TxPICLKSEL GND GND TxLOCKERR A RxDout0P RxDout0N GND RxDout1P RxDout1N GND RxDout2P RxDout2N GND RxDout3P RxDout3N GND RxREFCLKP RxREFCLKN GND TxDin0P TxDin0N GND TxDin1P TxDin1N GND TxDin2P TxDin2N GND TxDin3P TxDin3N GND TxREFCLKP TxREFCLKN GND
RxRATESEL0 RxRATESEL1 +3.3V +3.3V Rx_Reset +3.3V +3.3V NUC NUC NUC FFU FFU NUC NUC NUC NUC FFU RxALMINT NUC TxALMINT FFU NUC FFU FFU
9 RxMUTEPOCLK 10 11 -5.2V -5.2V
12 RxMUTEMCLK 13 14 15 16 17 18 19 20 -5.2V -5.2V I2CCLOCK +5V +5V I2CDATA +3.3V +3.3V
21 TxRATESEL0 TxRATESEL1 22 23 24 25 26 27 28 29 30 +3.3V +3.3V TxRESET -5.2V -5.2V TxFIFORES -5.2V -5.2V TxFIFOERR FFU FFU NUC NUC NUC NUC FFU TxTRACE NUC
FFU: Reserved for Future Use
NUC: No Use Connection
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Mechanical Design Diagram
The mechanical design diagram is shown in Figure 2.
(Bottom View)
All dimensions are in inch, if there is no special note.
Figure 2, Mechanical Diagram
Ordering Information
FAM
Wavelength 7: DWDM Wavelength Function (300-pin transponder) 0: Without jitter filter 1: With jitter filter
Distance Receptacle 40: 40km C: LC 80: 80km S: SC Package F: FC T: 300-PIN MSA M: MU
Version Code B: B version
DWDM Wavelength xxxx: The last four digits of ITU frequency (9340 indicates 193.40THz)
Data rate X1: Multi-rate from 9.95328G to 10.709G (without jitter filter) X2: 9.95328G X3: 10.3125G X4: 10.644G X5: 10.709G XA: 9.95328G&10.709G (dual jitter-filter) XB: 9.95328G&10.3125G (dual jitter-filter)
Part No. FAM-70X1S-T40-xxxx FAM-70X1S-T40B-xxxx
Product Description DWDM wavelength, 100G grid, 10Gbps, 40km laser, PIN receiver, 300-Pin, SC connector, without jitter filter, -5C~+70C, DWDM wavelength, 100G grid, 10Gbps, 40km laser, APD receiver, 300-Pin, SC connector, without jitter filter, -5C~+70C,
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FAM-70X1S-T80-xxxx FAM-70X1S-T80B-xxxx
DWDM wavelength, 100G grid, 10Gbps, 80km laser, APD receiver, 300-Pin, SC connector, without jitter filter, -5C~+70C, DWDM wavelength, 100G grid, 10Gbps, 80km laser, PIN receiver, 300-Pin, SC connector, without jitter filter, -5C~+70C,
Related Documents
For further information, please refer to the following documents: Application Note for Fiberxon 10G Transponder I2C Serial Interface Specifications Reference Document for 300 pin Multi Source Agreement for 10 Gigabit Transponders (SERDES Transceivers), Edition 4, August 14, 2002 I2C Reference Document for 300-PIN MSA 10G and 40G Transponders, Edition 4, July 24, 2002.
Obtaining Document
You can visit our website: http://www.fiberxon.com Or contact with Fiberxon, Inc. America Sales Office listed at the end of documentation to get the latest documents. (c) Copyright Fiberxon Inc. 2005 All Rights Reserved. All information contained in this document is subject to change without notice. The products described in this document are NOT intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. The information contained in this document does not affect or change Fiberxon's product specifications or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of Fiberxon or third parties. All information contained in this document was obtained in specific environments, and is presented as an illustration. The results obtained in other operating environment may vary. THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN "AS IS" BASIS. In no event will Fiberxon be liable for damages arising directly from any use of the information contained in this document. Contact U.S.A. Headquarter: 5201 Great America Parkway, Suite 340 Santa Clara, CA 95054 U. S. A. Tel: 408-562-6288 Fax: 408-562-6289 Or visit our website: http://www.fiberxon.com
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